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Current Research Projects

 

Lab Mission Statement: Our laboratory works on advancing and scaling computing technologies with particular emphasis on physical synthesis and implementation methodologies. We currently work on

• Enabling emerging technologies (3D integration - Project 1) to provide sustained scalable computing power beyond planar integration.
• Addressing major hurdles to scalabilty such as extreme variability (Project 2) and elevated on-chip temperatures (Project 3).

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Project 1. Yield management and Cost-effective design techniques for 3D integrated circuits

Project supported by a generous gift from Qualcomm Corporation.

Publications

• [P3] S. Reda, G. Smith and L. Smith, "Maximizing the Functional Yield of Wafer-Wafer 3D Integration," to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
• [P2] C. Ferri, S. Reda and R. I. Bahar, "Parametric Yield Management for 3D ICs: Models and Strategies for Improvement,"ACM Journal on Emerging Technologies in Computing Systems , Special Issue on 3D ICs, 4(4), pp. 19:1 - 19:22, 2008.
• [P1] C. Ferri, S. Reda and R. I. Bahar, "Strategies for Improving the Parametric Yield and Profits of 3D ICs," Proc. International Conference on Computer-Aided Design, 2007, pp. 220-226.

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PROJECT 2. Modeling and analysis of process variations in sub-100nm CMOS circuits

Project supported by equipment donation from Altera Corporation

Publications

• [P2] S. Reda and S. Nassif, "Analyzing the Impact of Process Variations on Parametric Measurements: Novel Models and Applications," to appear in Design, Automation, Test in Europe, 2009.
• [P1] B. Hargreaves, H. Hult and S. Reda, "Within-die Process Variations: How Accurately can They Be Statistically Modeled?" Proc. Asia-Pacific Design Automation Conference, 2008, pp. 524-530. Best Paper Candidate.

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PROJECT 3. Thermal/PERFORMANCE management for multi-core processors

Publications

• [P1] M. Kadin and S. Reda, "Frequency and Voltage Planning for Multi-Core Processors Under Thermal Constraints," International Conference on Computer Design, pp. 463 - 470, 2008.
• [P2] M. Kadin and S. Reda, "Frequency Planning for Multi-Core Processors Under Thermal Constraints," International Symposium on Low Power Electronics and Design, pp. 213-216, 2008.
• [P3] D. Meisner and S. Reda, "Hardware Libraries: An Architecture for Economic Acceleration in Soft Multi-Core Environments," Proc. International Conference on Computer Design, 2007, pp. 189-196.

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Archived research Projects

• Placement and routing techniques for application specific integrated circuits

• Design automation techniques for DNA arrays (gene chips)

• Test and verification of integrated circuits